The present invention relates in general to a technique for use in fabricating a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique applicable effectively to an inspection process in which solder printed on a substrate is inspected in three dimensions (hereinafter referred to as “3D”) and in two dimensions (referred to as “2D” hereinafter).
For example, in connection with the fabrication of a semiconductor integrated circuit device, solder inspecting techniques are described in Japanese Unexamined Patent Publication No. 2000-193432 (Patent Literature 1) and No. 2000-22326 (Patent Literature 2).
Patent Literature 1, in connection with a technique for measuring bumps formed on a silicon wafer, describes a technique that is used for measuring the height and area of solder in 2D and 3D and in which a 2D measurement step is added before or after a series of 3D measurements.
Patent Literature 2 describes a solder inspecting technique in which a pad surface on a substrate is measured in 2D, and whether the state of solder is good or bad is detected from the result of the measurement and also from the state detected after application of solder on the pad surface. Then, if the pad surface is error-free, it can be further inspected in 3D as a second step.
[Patent Literature 1]    Japanese Unexamined Patent Publication No. 2000-193432
[Patent Literature 2]    Japanese Unexamined Patent Publication No. 2000-22326